A plasma addressed display device in which a plasma cell and the electro-optical display cell are layered together with a dielectric sheet in between, has been previously disclosed in U.S. Pat. No. 4,896,149 to Buzak (Issue date: Jan. 23,1990), U.S. Pat. No. 5,077,553 to Buzak (Issue date: Dec. 31, 1991), and U.S. Pat. application Ser. No. 07/837,961 for an Electro Optical Device, filed by Shigeki Miyazaki on Feb. 20, 1992. The disclosure of the three above noted references are hereby incorporated herein. FIG. 1 and FIG. 2 illustrate a construction of such plasma addressed display device 100.
In FIG. 1 and FIG. 2, the plasma addressed display device 100 is constructed of a flat panel in which the electro-optical display cell 1 and the plasma cell 2 are layered together with the dielectric sheet 3 positioned between them. The dielectric sheet 3 is made up of laminate glass and/or other materials. In order to allow the display cell 1 to be driven, it is preferable for such dielectric sheet 3 to be formed as-thickly as possible, for example, a thickness of 50 .mu.m.
The display cell 1 is comprised of an upper glass substrate (upper substrate) 4. Inside the upper substrate 4, a number of data electrodes 5 made of transparent conductive material are positioned in such a way as to form parallel vertical rows. The upper substrate 4 is separated from the dielectric sheet 3 at a predetermined distance by spacers 6. The space between the upper substrate 4 and the dielectric sheet 3 is filled with liquid crystal, which forms a liquid crystal layer 7.
The plasma cell 2 incorporates a lower glass substrate (lower substrate) 8. Inside the lower substrate 8, a number of anode electrodes 9A and cathode electrodes 9K, which constitute plasma electrodes, are alternately positioned in parallel columns. Each electrodes 9A and 9K has a barrier rib 10 on its upper side. The tops of each of the barrier ribs 10 are in contact with the underside of the dielectric sheet 3.
A frit seal portion 11 is located on the circumference of the lower substrate 8 and attaches the lower substrate 8 to the dielectric sheet 3 in an air-tight fashion. The space between the lower substrate 8 and the dielectric sheet 3 is filled with an ionizable gas.
The spaces between the lower substrate 8 and the dielectric sheet 3 form discharge channels 12 which run in parallel rows to each other and which form right angles with the data electrodes 5. Pixels 13 are provided where the discharge channels 12 intersect with the data electrodes 5 as shown in FIG. 3.
In such construction, when a predetermined voltage is applied between the anode electrodes 9A and the cathode electrode 9K corresponding to a specified pair of discharge channels 12, the gas in the pair of the discharge channel 12 is ionized, generating a plasma discharge, at which point the discharge channel 12 is held at anode electric potential. In this situation, when a write data voltage is applied to the data electrode 5, the write data voltage is written through the dielectric sheet 3 onto the liquid crystal layer 7 for each of the pixels 13, which pixels are arranged along a column corresponding to the pair of the discharge channels 12. When the plasma discharge is completed, the discharge channel 12 changes to a floating electric potential, and the liquid crystal layer 7 for each pixel 13 holds the written data voltage until the next writing period (for example, one field later or one frame later). In such process, the discharge channel 12 acts as a sampling switch, and the liquid crystal layer 7 of each of the pixels 13 acts as a sampling capacitor.
A display is produced on a pixel basis from the action of the liquid crystal due to the data voltage which is written onto the liquid crystal layer 7 for each of the pixels 13. Accordingly, a two-dimensional image can be displayed by scanning successively along a row of a pair of the discharge channels 12 in which the plasma discharge is generated, writing a write data voltage onto the liquid crystal layer 7 for the pixels 13 arranged along a column.
FIG. 4 illustrates in a block diagram form a construction of the plasma addressed display device 100 described above. In FIG. 4, the same reference numbers have been employed to designate like portions in FIG. 1 and FIG. 2. Reference numeral 21 denotes a liquid crystal driver, which receives video data "DATA". The liquid crystal driver 21 simultaneously outputs the data voltages DS(1) to DS(m) for pixels which form a line during each horizontal period. These data voltages DS(1) to DS(m) for pixels are supplied via buffers 22(1) to 22(m), respectively, to the data electrodes 5(1) to 5(m), respectively.
The operation of the liquid crystal driver 21 is controlled by a controller 23. A horizontal synchronizing signal HD and a vertical synchronizing signal VD are supplied as synchronizing reference signals to the controller 23. This controller 23 also controls the operations of an anode driver 24 and a cathode driver 25 described below.
Reference numeral 24 denotes the anode driver, which supplies an anode voltage VA as a reference voltage to anode electrodes 9A(l) to 9A(n) which are all connected to the anode driver 24. Reference numeral 25 denotes the cathode driver, which during each horizontal period successively supplies cathode voltages VK(1) to VK(n-1) which are equal to voltage differences between an anode electric potential and a predetermined electric potential, to cathode electrodes 9K(1) to 9K(n-1). This process allows the plasma discharge to be generated during each horizontal period successively in each pair of the discharge channels 12 corresponding to each of the cathode electrodes 9K(1) to 9K(n-1), so that the pairs of discharge channels 12 for writing data voltages DS(1) to DS(m) onto the liquid crystal layers 7 for the pixels arranged in horizontal columns, are scanned successively along a vertical row.
The cathode voltage to be applied to the cathode electrode 9K and the data voltage DS to be applied to the data electrode 5 are, respectively, described below. FIG. 5A to 5D are the cathode voltages VK(a) to VK(a+3) to be applied to the serial cathode electrodes 9K(a) to 9K(a+3), respectively, and FIG. 5E is the data voltage DS to be applied to the specified data electrode 5. The cathode voltages VK(a) to VK(a+3), which are equal to the voltage differences between the anode electric potential and the predetermined electric potential, are applied during each horizontal period (1H) for each frame to the cathode electrodes 9K(a) to 9K(a+3), respectively. Thus, the discharge channels 12 in which the plasma discharge is generated, are successively scanned along the vertical row. In addition, during each horizontal period and for each frame the data voltage DS is inverted in polarity in accordance with the anode electric potential, so that the liquid crystal layer 7 is driven by an alternating current.
In the plasma addressed display device 100 described above, the lower face of the dielectric sheet 3 (the side of the plasma cell 2) is charged by ions and electrons generated by the plasma discharge (which is a DC discharge), causing the data voltage DS to be written onto the dielectric sheet 3. In a device which writes the data by DC discharge such as this, it is difficult in principle to make the discharge current density uniform throughout the discharge channel and to provide a stable display image on the whole screen, because of the condition of the surface of the plasma electrodes (the anode electrode 9A and the cathode electrode 9K), drops in voltage caused by the discharge current, dispersion in the construction, and the electric potential of the data electrode.
For example, because the area where the discharge is generated is easily discharged by a positive feedback due to the DC discharge, the discharge is dispersed. Moreover it is difficult to generate the discharge in places because of a drop in voltage from the discharge flow. When the data voltage DS is equal in polarity to the cathode voltage and the anode electric potential (which is the reference electric potential) which are used as discharge drive voltages, the electric field in the discharge channel 12 is weakened, and such weakness inhibits generation of the discharge.
Further, the anode electrode 9A or the cathode electrode 9K may be disconnected due, to sputtering of the ions and the electrons generated by the plasma discharge because the electrodes are not covered with dielectric material. Also, the degree of transmission may be adversely affected by metal fragments scattered by such sputtering. Additionally, since a discharge luminescence caused by the DC discharge is maintained, the contrast for the display is lost somewhat due to the brightness of the screen.